ACM Ultra-C 3xx with SAPS Technology

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Single Wafer Wet Etch & Clean Systems

Product Description:

ACM’s Smart Megasonix™— the industry’s most advanced cleaning

For all of these reasons ACM has developed innovative new single-wafer wet cleaning technologies and advanced wafer cleaning systems that can be used at existing and future process nodes across the range of processing steps — to achieve thorough, comprehensive cleaning, evenly across the wafer, and without damage to device features. These proprietary new ACM technologies are able to precisely control both the power intensity and the distribution of megasonic cleaning – with dramatically positive effect.

SAPS cleaning technology: for flat and patterned wafers – to 22nm and beyond

ACM’s proprietary Space Alternated Phase Shift (SAPS™) technology employs alternating phases of megasonic waves to deliver megasonic energy to flat and patterned wafer surfaces in a highly uniform manner on a microscopic level. This enables it to remove random defects across an entire wafer much more efficiently than conventional jet spray processes. SAPS technology has demonstrated its advanced cleaning capabilities as nodes shrink from 65nm to 22nm and even beyond, for which jet spray technology is becoming less effective. Moreover, users of SAPS equipment have already expanded their application of ACM tools, adding cleaning to more processing steps to increase yields and reduce chemical usage

Major Benefits

  • High Particle Removal (PRE) efficiency at smaller particle size
  • No cross contamination
  • Low Cost of Ownership
  • Remove residues, resulting in higher yields

Features & Specifications

8” and 12” wafer available

  • Main Hardware Configuration:
    • 4, 8 and 12 chamber platform
    • 4 load ports
    • EFEM with aligner and robot
    • 1 EFFM robot
    • 2 process robots
    • SAPS Megasonics, 0-1.5W/cm2, high PRE
    • Uniform Megasonic power density: WIWNU < 2%
    • Dry method : N2 spin dry or liquid IPA
    • Chemicals Upto 5 chemicals can be run DIO3,SC1,SC2, dHF, F -water, IPA, chemicals can run to drain or be recycled
  • Process Capabilities:
    • Particle Performance: ≤ 10 @30nm
    • Metal Contamination : ≤ 1X1010 atoms/cm2
    • Throughput: 225 wph (90sec recipe) with 8 chamber

SAPS wafer cleaning applications

  • Post CMP
  • Post Hard Mask Deposition: As part of the photolithographic patterning process, hard masks have been developed to etch high-aspect-ratio features of advanced chips that traditional masks cannot tolerate. SAPS cleaning technology can be employed following each deposition step involving hard masks that use nitride, oxide or carbon based materials to achieve higher etch selectivity and resolution.
  • Interconnects and Barrier Metals: SAPS technology can improve the removal of residues and other random defects from interconnects with deep contacts or vias during the chip fabrication process:
  • Post Contact/Via Etch/TSV: Etching processes are commonly used to create patterns of high-density contacts and vias. SAPS technology can be applied after each such etching process to remove random defects that could otherwise lead to electrical shorts.
  • Pre Barrier Metal Deposition: Copper wiring requires metal diffusion barriers at the top of via holes to prevent electrical migration during operation leading to leakage or opens. SAPS technology can be applied prior to deposition of barrier metal to remove residual oxidized copper, which otherwise would adhere poorly to the barrier and impair performance.
  • Recycled Test Wafers: Manufacturers routinely process wafers through a limited portion of the fabrication steps in order to evaluate the health as well as use wafers for non-product purposes such as inline monitoring. These wafers used for purposes other than manufacturing revenue products are known as test wafers, and manufacturers seek to re-use a test wafer for more than one test. As test wafers are recycled, SAPS technology can be applied to reduce random defect levels of a recycled wafer.
  • Final Clean for Prime Wafers: Wafer manufacturers routinely process wafers through many CMP and polishing steps to obtain a prime wafer to meet customer specifications. These wafers have very tight particle and metal specifications. At post CMP steps and final clean the use of SAPS technologycan be applied to reduce defect levels on a Prime wafer.

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